Semiconductor important process flow of packaging
Semiconductor important process flow of packaging
Electronic packaging is an indispensable process after the completion of integrated circuit chip production, is the bridge from device to system. The production link of packaging has a great impact on the quality and competitiveness of microelectronic products. According to the current international popular opinion, in the microelectronic device
According to the current international popular opinion, in the microelectronic devices, design accounts for one-third of the overall cost, chip production accounts for one-third, and packaging and testing also accounted for one-third of the world can be said to be one of the three.
Packaging research in the global scope of the development is so rapid, and the challenges and opportunities it faces since the advent of electronic products have never been encountered; packaging involves a wide range of issues, but also many other areas of rare, it is from the material to process, from inorganic to polymer, from large-scale production equipment to computational mechanics, etc., a comprehensive and very strong new discipline.
It is a new high-tech discipline with strong integration.
What is packaging
The original definition of encapsulation is to protect the circuit chip from the influence of the surrounding environment (including physical and chemical influences).
Chip packaging
Chip packaging is the use of (film technology) and (microfabrication technology), the chip and other elements in the frame or substrate layout, paste fixed and connected to lead out the terminals
And through the plastic insulation medium potting fixed, constitute the overall structure of the process.
Electronic packaging engineering: the substrate, chip packaging body and discrete device
Elements, such as substrates, chip packages and discrete devices, according to the requirements of the electronic machine for connection and assembly, to achieve certain electrical and physical properties, transformed into a machine or system with the form of the machine or device.
Integrated circuit packaging can protect the chip from or less affected by the external environment, and provide a good working condition, in order to make the integrated circuit has a stable, normal function.
Chip packaging can realize power distribution; signal distribution; heat dissipation channel; mechanical support; environmental protection.
Levels of Packaging Technology
The first level, also known as the chip level of packaging, refers to the integrated circuit chip and packaging substrate
or pin frame between the paste fixed circuit wiring and encapsulation protection process, so that it becomes easy to pick and place transportation, and can be connected with the next level of assembly of the module components.
At the second level, the process of forming an electronic card from several packages completed at the first level and other electronic components.
At the third level, the process of combining several second level packages to form a circuit card into a component or subsystem on a main circuit board.
The fourth level, several subsystems will be assembled into a complete electronic product process.
They are, in order, the chip interconnect level (zero-level package), a package (multi-chip assembly), the second level of packaging (PWB or card), the third level of packaging (motherboard).
Categorization of Packages
According to the number of integrated circuit chips combined in the package, the chip package can be divided into: single-chip package and multi-chip package two categories;
According to the sealing material distinction, can be divided into polymer materials
and ceramic-based categories;
According to the device and the circuit board interconnection, the package can be distinguished into two categories: pin insertion type and surface mount type;
According to the pin distribution pattern distinction, packaging components have a single side of the pin, double side of the pin, four side of the pin, the bottom of the pin four kinds.
Common single-sided pins have a single-row package and cross-pin package;
Bilateral pin components have dual-row package miniaturization package;
Four-side pins have four-side flat package;
Bottom pins have a metal can type and point array package.
Package terminology
SIP: single in-line package SQP: miniaturized package MCP: metal can package
DIP: Dual In-line Package CSP: Chip Size Package
QFP: Quad Flat Packaging
PGA: Dot-Grid
BGA: Ball Grid Array Package LCCC: Leadless Ceramic Chip Carrier
Stages of development of packaging technology
Semiconductor industry
There are different standards for the division of the level of chip packaging technology, the more common domestic standard is to take the packaging chip and substrate connection to divide, in general, the development of IC packaging technology can be divided into four stages:
The first stage: before the 1980s (jack original era).
The main technology of packaging is pin-on-pin (PTH), which is characterized by the jack mounted on the PCB, the main form of SIP, DIP, PGA, their shortcomings are the density, frequency is difficult to improve, and difficult to meet the requirements of efficient automated production.
The second stage: the mid-1980s (surface mount era).
Phase III: the 1990s saw a second leap into the area array packaging era.
The main forms of packaging at this stage are solder ball array package (BGA), chip size package (CSP), leadless quad flat package (PQFN), multi-chip components (MCM). BGA technology makes the pins that occupy a large volume and weight in the package are replaced by the solder ball, and the connecting distance between the chip and the system is greatly shortened, and the successful development of the BGA technology makes the package finally catching up with chip development, and CSP technology solves the fundamental contradiction of the long-existing small chip and large package. The successful development of BGA technology, so that has been lagging behind the development of the chip package finally keep pace with the development of the chip, CSP technology to solve the long-standing fundamental contradiction between the chip small and large package, triggering a revolution in integrated circuit packaging technology.
Phase IV: into the 21st century, ushered in the era of microelectronic packaging technology stacked package, which has revolutionized the concept of packaging, from the original concept of packaging components evolved into packaging systems.
At present, the mainstream of global semiconductor packaging is in the third stage of maturity, PQFN and BGA and other major packaging technologies for mass production, some products have begun in the development of the fourth stage.
Microelectromechanical systems
(MEMS) chips are stacked three-dimensional package.
Packaging process
1. The encapsulation process can be generally divided into two parts: the process steps before encapsulation with plastic become the front operation, and the process steps after molding become the back operation.
2. The basic process of chip encapsulation technology, wafer thinning, wafer cutting, chip mounting, chip interconnect, molding technology, deburring flying edges, cutting rib molding, soldering and coding processes.
3. The backside thinning technology of silicon wafer mainly includes grinding, lapping, chemical-mechanical polishing, dry polishing, electrochemical corrosion, wet corrosion, plasma-enhanced chemical corrosion, atmospheric pressure plasma corrosion and so on.
4. Scribe first and then thin: before the backside grinding, the front side of the wafer will be cut with a certain depth of incision, and then the backside grinding is carried out.
5. Thinning paddle: before thinning, first cut the incision with mechanical or chemical way, then thin to a certain thickness by grinding method after using ADPE corrosion technology to remove the remaining processing volume to realize the automatic separation of bare chips.
6. Chip mounted in four ways: eutectic paste method, welding paste method, conductive adhesive paste method, and glass adhesive paste method. Eutectic paste method: the use of gold - silicon alloy (generally 69% Au, 31% of Si), 363 degrees when the eutectic fusion reaction to make the IC chip paste fixed.
7. In order to obtain the best eutectic mounting method, the back of the IC chip is usually first plated with a layer of gold film or in the substrate chip carrier first implanted on the pre-chip.
8. Common methods of interconnecting chips are wire bonding, TAB and flip chip bonding.
9. Wire bonding techniques include ultrasonic bonding, thermocompression bonding, and thermal ultrasonic bonding.
10. TAB key technologies: 1, chip bump production technology, 2, TAB carrier tape production technology, 3, carrier tape leads and chip bumps within the lead welding and carrier tape outside the lead welding technology.
11. Bump chip production process, the formation of bump technology: evaporation / sputtering coated point production method, electroplating bump production method to set the ball and template printing production, solder bump hair, chemical plating coated point production method, playing the ball bump production method, laser method.
12. Plastic packaging molding technology, 1, transfer molding technology, 2, spray molding technology, 3, pre-molding technology, but the most important technology is the transfer molding technology, transfer technology using materials generally thermosetting polymers.
13. Thinned chip has the following advantages: 1, thin chip is more conducive to heat dissipation; 2, reduce the chip package volume; 3, improve mechanical properties, wafer thinning, the better its flexibility, the stress caused by the impact of external forces is also smaller; 4, the thinner the thickness of the wafer, the shorter the connection between the components, the component on-resistance will be the lower the signal delay time is shorter, so as to achieve a higher level of performance; 5, to reduce the scribe Thinning the processing volume and then cut, you can reduce the amount of scratch processing, reduce the incidence of chip chipping.
14. Wave Soldering: The process of wave soldering includes fluxing, preheating, and passing the PCB board on a solder wave, relying on the joint action of surface tension and capillary phenomenon to bring the flux to the PCB board and component pins to form a solder joint.
Wave soldering is the molten liquid solder, with the help of the pump, in the solder tank liquid surface to form a specific shape of the solder wave, loaded with components of the PCB placed on the conveyor chain, by a particular angle and a certain depth of entry through the solder wave to achieve the solder joints of the welding process.
Reflow soldering: by pre-positioned in the PCB soldering part of the application of the appropriate amount and appropriate form of solder, and then affixed to the surface assembly components, and then through the re-melting of pre-allocated to the printed circuit board pads on the solder paste to achieve the surface assembly components solder ends or pins and printed circuit board pads between the mechanical and electrical connection between a group or point-by-point soldering process.
15. Play wire bonding (WB): the fine metal wire or metal strip in order to play in the chip and pin frame or package substrate solder pads to form circuit interconnections. Wire bonding technologies include ultrasonic bonding, thermocompression bonding, and thermal ultrasonic bonding.
Carrier tape automatic bonding (TAB): the chip solder area and the electronic packaging shell of the I / O or substrate metal wiring solder area with a lead pattern metal foil wire connection technology process.
Flip Chip Bonding (FCB): A method of directly interconnecting the chip solder area to the substrate solder area with the chip face down.
16. Chip interconnect: the chip solder area and the electronic packaging shell of the I / O or substrate metal wiring solder area connected, only to realize the chip and packaging structure of the circuit connection to play the existing function.
Advanced Packaging Technology SIP
With the era of the Internet of Things and global terminal electronic products are gradually moving towards multi-functional integration and low-power design, which makes it possible to integrate multiple bare crystals in a single package SiP technology is increasingly concerned. In addition to the existing major packaging and testing companies actively expanding SiP manufacturing capacity, wafer foundries and IC substrate manufacturers are also competing to invest in this technology to meet market demand.
Definition of SIP
According to the definition of the International Semiconductor Routing System (ITRS), SiP is a system or subsystem that combines multiple active electronic components with different functions and optional passive devices, as well as other devices such as MEMS or optical devices, preferentially assembled together to achieve a certain function in a single standard package.
Therefore, architecturally, SiP is the integration of multiple functional chips, including processors, memories, and other functional chips, into a single package to realize a basically complete function.
Definition of SOC
The integration of ICs with different functions into a single chip. By this method, not only the size can be reduced, but also the distance between different ICs can be narrowed, and the computational speed of the chip can be increased.SoC is called System-on-Chip, or System-on-Chip, which means that it is a product, an integrated circuit with a dedicated target, which contains a complete system with embedded software in its entirety. At the same time, it is a technology that enables the entire design process, starting from defining the system functionality to dividing the software/hardware and completing the design.
As packaging technology continues to evolve, coupled with the trend toward thinner, lighter and shorter end-products, the demand for SiPs is gradually increasing.
The SiP production line must be composed of an ecosystem of substrates, wafers, modules, packaging, testing, and system integration in order to develop smoothly. On the contrary, without a complete ecosystem, it is difficult to promote the concrete realization of SiP technology.
As SiP technology can be packaged in a single package with a variety of chips to form a system of its own, it has high integration and miniaturization characteristics, and is suitable for use in small size, multi-functional, low-power and other characteristics of electronic products.
In terms of various applications, if the original independent package components are integrated with SiP technology, it can reduce the size of the package to save space and shorten the connection line between the components to reduce the resistance and enhance the electrical effect, ultimately presenting the advantages of tiny packages to replace the large-scale circuit boards, but still maintain the original function of each chip. Therefore, the high integration and miniaturization features make SiP become the development trend of packaging technology in recent years.
In addition, because SiP is the relevant circuitry to the package body complete package, therefore can increase the circuit board resistance to chemical corrosion and stress (Anti-stress) ability to improve the overall reliability of the product, the product life can also be enhanced.
Compared to SoC, SiP does not require new state chip design and validation, but rather the existing different functions of the chip, the integration of packaging technology.
Roughly speaking, the basic packaging technologies commonly used in SiP at this stage include Package on Package (PoP) technology, which is commonly used in smart phones, where logic ICs and memory ICs are stacked in packages. Embedded technology, in which active and passive components are embedded in the substrate, as well as Multi-Chip Package (MCP), Multi-Chip Module (MCM), Stacking Die, PiP, TSV 2.5D ICs, and TSV 3D ICs, also belong to the category of SiP technology.
Smartphones play a major role in driving SiP growth.
Compared with the PC era, the demand for SiP in mobile device products is more common. In the case of smart phones, Internet access is already a basic feature, so Wi-Fi modules related to wireless networks will be integrated with SiP technology.
Based on the security and confidentiality considerations developed by the fingerprint recognition function, its related chip package also needs SiP to help integrate and reduce the space, so that the fingerprint recognition module began to become a SiP widely used market; in addition, pressure touch is also one of the emerging features of smart phones, built-in pressure touch module (Force Touch) is the need for SiP technology to assist.
In addition, the application processor (AP) and memory for the integration of processor modules, as well as with the sensing-related MEMS modules, etc., is also the application of SiP technology.
Wearable devices / Internet of Things to drive the demand for SiP rise
The development of global terminal electronic products is constantly moving towards the trend of thin, light, multi-functional, and low power consumption, and the growth potential of SiP is increasing. 2015 Apple Watch and other wearable products were introduced, SiP technology has been expanded and applied to wearable products.
In addition, under the trend of the Internet of Everything, it will inevitably be combined with a variety of mobile devices, wearable devices, intelligent transportation, intelligent medical care, and smart home network, multi-functional heterogeneous chip integration is expected to have a huge demand for low-power consumption will also be an important trend.
Packaging technology as an important foundation of the information industry in the product plays a big role. Specifically, there is a huge market for packaging, which determines product performance, reliability, life, cost and so on. Competition in the modern electronic information industry in a sense is mainly electronic packaging industry competition, which to a certain extent determines the level of modern industrialization.
According to the current international popular opinion, in the microelectronic devices, design accounts for one-third of the overall cost, chip production accounts for one-third, and packaging and testing also accounted for one-third of the world can be said to be one of the three.
Packaging research in the global scope of the development is so rapid, and the challenges and opportunities it faces since the advent of electronic products have never been encountered; packaging involves a wide range of issues, but also many other areas of rare, it is from the material to process, from inorganic to polymer, from large-scale production equipment to computational mechanics, etc., a comprehensive and very strong new discipline.
It is a new high-tech discipline with strong integration.
What is packaging
The original definition of encapsulation is to protect the circuit chip from the influence of the surrounding environment (including physical and chemical influences).
Chip packaging
Chip packaging is the use of (film technology) and (microfabrication technology), the chip and other elements in the frame or substrate layout, paste fixed and connected to lead out the terminals
And through the plastic insulation medium potting fixed, constitute the overall structure of the process.
Electronic packaging engineering: the substrate, chip packaging body and discrete device
Elements, such as substrates, chip packages and discrete devices, according to the requirements of the electronic machine for connection and assembly, to achieve certain electrical and physical properties, transformed into a machine or system with the form of the machine or device.
Integrated circuit packaging can protect the chip from or less affected by the external environment, and provide a good working condition, in order to make the integrated circuit has a stable, normal function.
Chip packaging can realize power distribution; signal distribution; heat dissipation channel; mechanical support; environmental protection.
Levels of Packaging Technology
The first level, also known as the chip level of packaging, refers to the integrated circuit chip and packaging substrate
or pin frame between the paste fixed circuit wiring and encapsulation protection process, so that it becomes easy to pick and place transportation, and can be connected with the next level of assembly of the module components.
At the second level, the process of forming an electronic card from several packages completed at the first level and other electronic components.
At the third level, the process of combining several second level packages to form a circuit card into a component or subsystem on a main circuit board.
The fourth level, several subsystems will be assembled into a complete electronic product process.
They are, in order, the chip interconnect level (zero-level package), a package (multi-chip assembly), the second level of packaging (PWB or card), the third level of packaging (motherboard).
Categorization of Packages
According to the number of integrated circuit chips combined in the package, the chip package can be divided into: single-chip package and multi-chip package two categories;
According to the sealing material distinction, can be divided into polymer materials
and ceramic-based categories;
According to the device and the circuit board interconnection, the package can be distinguished into two categories: pin insertion type and surface mount type;
According to the pin distribution pattern distinction, packaging components have a single side of the pin, double side of the pin, four side of the pin, the bottom of the pin four kinds.
Common single-sided pins have a single-row package and cross-pin package;
Bilateral pin components have dual-row package miniaturization package;
Four-side pins have four-side flat package;
Bottom pins have a metal can type and point array package.
Package terminology
SIP: single in-line package SQP: miniaturized package MCP: metal can package
DIP: Dual In-line Package CSP: Chip Size Package
QFP: Quad Flat Packaging
PGA: Dot-Grid
BGA: Ball Grid Array Package LCCC: Leadless Ceramic Chip Carrier
Stages of development of packaging technology
Semiconductor industry
There are different standards for the division of the level of chip packaging technology, the more common domestic standard is to take the packaging chip and substrate connection to divide, in general, the development of IC packaging technology can be divided into four stages:
The first stage: before the 1980s (jack original era).
The main technology of packaging is pin-on-pin (PTH), which is characterized by the jack mounted on the PCB, the main form of SIP, DIP, PGA, their shortcomings are the density, frequency is difficult to improve, and difficult to meet the requirements of efficient automated production.
The second stage: the mid-1980s (surface mount era).
Phase III: the 1990s saw a second leap into the area array packaging era.
The main forms of packaging at this stage are solder ball array package (BGA), chip size package (CSP), leadless quad flat package (PQFN), multi-chip components (MCM). BGA technology makes the pins that occupy a large volume and weight in the package are replaced by the solder ball, and the connecting distance between the chip and the system is greatly shortened, and the successful development of the BGA technology makes the package finally catching up with chip development, and CSP technology solves the fundamental contradiction of the long-existing small chip and large package. The successful development of BGA technology, so that has been lagging behind the development of the chip package finally keep pace with the development of the chip, CSP technology to solve the long-standing fundamental contradiction between the chip small and large package, triggering a revolution in integrated circuit packaging technology.
Phase IV: into the 21st century, ushered in the era of microelectronic packaging technology stacked package, which has revolutionized the concept of packaging, from the original concept of packaging components evolved into packaging systems.
At present, the mainstream of global semiconductor packaging is in the third stage of maturity, PQFN and BGA and other major packaging technologies for mass production, some products have begun in the development of the fourth stage.
Microelectromechanical systems
(MEMS) chips are stacked three-dimensional package.
Packaging process
1. The encapsulation process can be generally divided into two parts: the process steps before encapsulation with plastic become the front operation, and the process steps after molding become the back operation.
2. The basic process of chip encapsulation technology, wafer thinning, wafer cutting, chip mounting, chip interconnect, molding technology, deburring flying edges, cutting rib molding, soldering and coding processes.
3. The backside thinning technology of silicon wafer mainly includes grinding, lapping, chemical-mechanical polishing, dry polishing, electrochemical corrosion, wet corrosion, plasma-enhanced chemical corrosion, atmospheric pressure plasma corrosion and so on.
4. Scribe first and then thin: before the backside grinding, the front side of the wafer will be cut with a certain depth of incision, and then the backside grinding is carried out.
5. Thinning paddle: before thinning, first cut the incision with mechanical or chemical way, then thin to a certain thickness by grinding method after using ADPE corrosion technology to remove the remaining processing volume to realize the automatic separation of bare chips.
6. Chip mounted in four ways: eutectic paste method, welding paste method, conductive adhesive paste method, and glass adhesive paste method. Eutectic paste method: the use of gold - silicon alloy (generally 69% Au, 31% of Si), 363 degrees when the eutectic fusion reaction to make the IC chip paste fixed.
7. In order to obtain the best eutectic mounting method, the back of the IC chip is usually first plated with a layer of gold film or in the substrate chip carrier first implanted on the pre-chip.
8. Common methods of interconnecting chips are wire bonding, TAB and flip chip bonding.
9. Wire bonding techniques include ultrasonic bonding, thermocompression bonding, and thermal ultrasonic bonding.
10. TAB key technologies: 1, chip bump production technology, 2, TAB carrier tape production technology, 3, carrier tape leads and chip bumps within the lead welding and carrier tape outside the lead welding technology.
11. Bump chip production process, the formation of bump technology: evaporation / sputtering coated point production method, electroplating bump production method to set the ball and template printing production, solder bump hair, chemical plating coated point production method, playing the ball bump production method, laser method.
12. Plastic packaging molding technology, 1, transfer molding technology, 2, spray molding technology, 3, pre-molding technology, but the most important technology is the transfer molding technology, transfer technology using materials generally thermosetting polymers.
13. Thinned chip has the following advantages: 1, thin chip is more conducive to heat dissipation; 2, reduce the chip package volume; 3, improve mechanical properties, wafer thinning, the better its flexibility, the stress caused by the impact of external forces is also smaller; 4, the thinner the thickness of the wafer, the shorter the connection between the components, the component on-resistance will be the lower the signal delay time is shorter, so as to achieve a higher level of performance; 5, to reduce the scribe Thinning the processing volume and then cut, you can reduce the amount of scratch processing, reduce the incidence of chip chipping.
14. Wave Soldering: The process of wave soldering includes fluxing, preheating, and passing the PCB board on a solder wave, relying on the joint action of surface tension and capillary phenomenon to bring the flux to the PCB board and component pins to form a solder joint.
Wave soldering is the molten liquid solder, with the help of the pump, in the solder tank liquid surface to form a specific shape of the solder wave, loaded with components of the PCB placed on the conveyor chain, by a particular angle and a certain depth of entry through the solder wave to achieve the solder joints of the welding process.
Reflow soldering: by pre-positioned in the PCB soldering part of the application of the appropriate amount and appropriate form of solder, and then affixed to the surface assembly components, and then through the re-melting of pre-allocated to the printed circuit board pads on the solder paste to achieve the surface assembly components solder ends or pins and printed circuit board pads between the mechanical and electrical connection between a group or point-by-point soldering process.
15. Play wire bonding (WB): the fine metal wire or metal strip in order to play in the chip and pin frame or package substrate solder pads to form circuit interconnections. Wire bonding technologies include ultrasonic bonding, thermocompression bonding, and thermal ultrasonic bonding.
Carrier tape automatic bonding (TAB): the chip solder area and the electronic packaging shell of the I / O or substrate metal wiring solder area with a lead pattern metal foil wire connection technology process.
Flip Chip Bonding (FCB): A method of directly interconnecting the chip solder area to the substrate solder area with the chip face down.
16. Chip interconnect: the chip solder area and the electronic packaging shell of the I / O or substrate metal wiring solder area connected, only to realize the chip and packaging structure of the circuit connection to play the existing function.
Advanced Packaging Technology SIP
With the era of the Internet of Things and global terminal electronic products are gradually moving towards multi-functional integration and low-power design, which makes it possible to integrate multiple bare crystals in a single package SiP technology is increasingly concerned. In addition to the existing major packaging and testing companies actively expanding SiP manufacturing capacity, wafer foundries and IC substrate manufacturers are also competing to invest in this technology to meet market demand.
Definition of SIP
According to the definition of the International Semiconductor Routing System (ITRS), SiP is a system or subsystem that combines multiple active electronic components with different functions and optional passive devices, as well as other devices such as MEMS or optical devices, preferentially assembled together to achieve a certain function in a single standard package.
Therefore, architecturally, SiP is the integration of multiple functional chips, including processors, memories, and other functional chips, into a single package to realize a basically complete function.
Definition of SOC
The integration of ICs with different functions into a single chip. By this method, not only the size can be reduced, but also the distance between different ICs can be narrowed, and the computational speed of the chip can be increased.SoC is called System-on-Chip, or System-on-Chip, which means that it is a product, an integrated circuit with a dedicated target, which contains a complete system with embedded software in its entirety. At the same time, it is a technology that enables the entire design process, starting from defining the system functionality to dividing the software/hardware and completing the design.
As packaging technology continues to evolve, coupled with the trend toward thinner, lighter and shorter end-products, the demand for SiPs is gradually increasing.
The SiP production line must be composed of an ecosystem of substrates, wafers, modules, packaging, testing, and system integration in order to develop smoothly. On the contrary, without a complete ecosystem, it is difficult to promote the concrete realization of SiP technology.
As SiP technology can be packaged in a single package with a variety of chips to form a system of its own, it has high integration and miniaturization characteristics, and is suitable for use in small size, multi-functional, low-power and other characteristics of electronic products.
In terms of various applications, if the original independent package components are integrated with SiP technology, it can reduce the size of the package to save space and shorten the connection line between the components to reduce the resistance and enhance the electrical effect, ultimately presenting the advantages of tiny packages to replace the large-scale circuit boards, but still maintain the original function of each chip. Therefore, the high integration and miniaturization features make SiP become the development trend of packaging technology in recent years.
In addition, because SiP is the relevant circuitry to the package body complete package, therefore can increase the circuit board resistance to chemical corrosion and stress (Anti-stress) ability to improve the overall reliability of the product, the product life can also be enhanced.
Compared to SoC, SiP does not require new state chip design and validation, but rather the existing different functions of the chip, the integration of packaging technology.
Roughly speaking, the basic packaging technologies commonly used in SiP at this stage include Package on Package (PoP) technology, which is commonly used in smart phones, where logic ICs and memory ICs are stacked in packages. Embedded technology, in which active and passive components are embedded in the substrate, as well as Multi-Chip Package (MCP), Multi-Chip Module (MCM), Stacking Die, PiP, TSV 2.5D ICs, and TSV 3D ICs, also belong to the category of SiP technology.
Smartphones play a major role in driving SiP growth.
Compared with the PC era, the demand for SiP in mobile device products is more common. In the case of smart phones, Internet access is already a basic feature, so Wi-Fi modules related to wireless networks will be integrated with SiP technology.
Based on the security and confidentiality considerations developed by the fingerprint recognition function, its related chip package also needs SiP to help integrate and reduce the space, so that the fingerprint recognition module began to become a SiP widely used market; in addition, pressure touch is also one of the emerging features of smart phones, built-in pressure touch module (Force Touch) is the need for SiP technology to assist.
In addition, the application processor (AP) and memory for the integration of processor modules, as well as with the sensing-related MEMS modules, etc., is also the application of SiP technology.
Wearable devices / Internet of Things to drive the demand for SiP rise
The development of global terminal electronic products is constantly moving towards the trend of thin, light, multi-functional, and low power consumption, and the growth potential of SiP is increasing. 2015 Apple Watch and other wearable products were introduced, SiP technology has been expanded and applied to wearable products.
In addition, under the trend of the Internet of Everything, it will inevitably be combined with a variety of mobile devices, wearable devices, intelligent transportation, intelligent medical care, and smart home network, multi-functional heterogeneous chip integration is expected to have a huge demand for low-power consumption will also be an important trend.
Packaging technology as an important foundation of the information industry in the product plays a big role. Specifically, there is a huge market for packaging, which determines product performance, reliability, life, cost and so on. Competition in the modern electronic information industry in a sense is mainly electronic packaging industry competition, which to a certain extent determines the level of modern industrialization.